As is known, frequency mismatches can occur whenever two clock sources are being used. In one example, there can be a frequency mismatch between a clock being used in the transmission of data and another clock being used in the receipt of data. This is seen, for instance, in conventional high-speed serial data links.
In one instance, a typical high-speed serial data link includes two transceivers, one on each end of the link. Each transceiver includes a serializing transmitter (a.k.a., a serializer) and a deserializing receiver (a.k.a., a deserializer). The serializer receives as input a parallel data byte, converts the data byte into a stream of serial data bits and transmits the serial data bits over a link to the deserializer in accordance with a transmit clock. The serial data includes the transmit clock information, which is extracted and used to recover the serial data stream and reassemble the parallel byte. Additionally, the deserializer uses the extracted clock information on the receive side as a receive clock to output the parallel data from the deserializer.
Since the extracted transmit clock becomes the receive clock, conventional high-speed serial data links automatically compensate for frequency differences between the transmit and receive clocks. However, this is not the case when the receive clock is not extracted from the transmit clock.
Thus, a need still exists for a mechanism to compensate for frequency differences when the transmit clock and receive clock are not from the same source. Further, a need exists for a mechanism that can dynamically adapt to frequency differences as those differences are detected. A further need exists for an adaptive filtering mechanism that enhances the accuracy and performance of digital phase-locked loops used in the extraction of data from serial data streams.